Commit 069044c1 authored by Michael Zehrer's avatar Michael Zehrer
Browse files

simplify startup and remove load/store exclusives, because they don't seem to...

simplify startup and remove load/store exclusives, because they don't seem to work properly without cache
parent e7a3d6b9
......@@ -66,48 +66,39 @@ uint32_t *createContext(uint32_t *stack, Task *task) {
int32_t atomicCompareAndExchange(int32_t *v, int32_t o, int32_t n) {
int32_t prev;
uint32_t res;
uint32_t flags;
asm volatile(
#if ARM_ARCH >= 7
"pldw [%[v_addr]]\n\t"
#else /* the 'pld'-instruction is available from ARMv5TE and above */
"pld [%[v_addr]]\n\t"
#endif
"mov %[res], #0\n\t"
"1: \n\t"
"ldrex %[prev], [%[v_addr]]\n\t"
"teq %[prev], %[o]\n\t"
"strexeq %[res], %[n], [%[v_addr]]\n\t"
"cmp %[res], #0\n\t"
"bne 1b\n\t"
: [res]"=&r"(res), [prev]"=&r"(prev), "+Qo"(*v)
: [v_addr]"r"(v), [o]"Ir"(o), [n]"r"(n)
: "cc");
"mrs %0, cpsr\n"
"cpsid i"
: "=r" (flags) : : "memory", "cc");
prev = *v;
if (prev == o)
*v = n;
asm volatile (
"msr cpsr_c, %0"
: : "r" (flags) : "memory", "cc");
return prev;
}
int64_t atomicCompareAndExchange(int64_t *v, int64_t o, int64_t n) {
int64_t prev;
uint32_t res;
uint32_t flags;
asm volatile(
#if ARM_ARCH >= 7
"pldw [%[v_addr]]\n\t"
#else /* the 'pld'-instruction is available from ARMv5TE and above */
"pld [%[v_addr]]\n\t"
#endif
"mov %[res], #0\n\t"
"1: \n\t"
"ldrexd %[prev], %H[prev], [%[v_addr]]\n\t"
"teq %[prev], %[o]\n\t"
"teqeq %H[prev], %H[o]\n\t"
"strexdeq %[res], %[n], %H[n], [%[v_addr]]\n\t"
"cmp %[res], #0\n\t"
"bne 1b\n\t"
: [res]"=&r"(res), [prev]"=&r"(prev), "+Qo"(*v)
: [v_addr]"r"(v), [o]"Ir"(o), [n]"r"(n)
: "cc");
"mrs %0, cpsr\n"
"cpsid i"
: "=r" (flags) : : "memory", "cc");
prev = *v;
if (prev == o)
*v = n;
asm volatile (
"msr cpsr_c, %0"
: : "r" (flags) : "memory", "cc");
return prev;
}
......
......@@ -60,27 +60,22 @@ reset_hdl:
#endif
reset_svc_mode:
bl os_mmu_disable
bl os_dCache_disable
bl os_iCache_disable
#if ARM_ARCH <= 7
bl os_branchPredictor_disable
#endif
ldr r0, =_exception_table
// Vector Base Address Register (VBAR) = r0
mcr p15, 0, r0, c12, c0, 0
// disable watchdog (just to be sure)
ldr r0, =POWER_MANAGEMENT_RSTC
ldr r1, =(POWER_MANAGEMENT_PASSWORD | POWER_MANAGEMENT_RSTC_RESET)
str r1, [r0]
// r1 = Vector Base Address Register (VBAR)
mrc p15, 0, r1, c12, c0, 0
// copy 0x40 bytes from 0x8000 to the address stored in VBAR (typically 0x0000)
mov r0, #0x8000
ldmia r0!,{r2,r3,r4,r5,r6,r7,r8,r9}
stmia r1!,{r2,r3,r4,r5,r6,r7,r8,r9}
ldmia r0!,{r2,r3,r4,r5,r6,r7,r8,r9}
stmia r1!,{r2,r3,r4,r5,r6,r7,r8,r9}
// set the stackpointer for the supervisor mode
mov sp, #0x4000
......@@ -129,40 +124,19 @@ bss_clear_loop:
b hang
hang:
bkpt #0
b hang
undefined_hdl:
// clear the exclusive monitor
clrex
bkpt #10
b hang
b undefined_hdl
prefetch_hdl:
// clear the exclusive monitor
clrex
bkpt #11
b hang
b prefetch_hdl
data_hdl:
// clear the exclusive monitor
clrex
bkpt #12
b hang
b data_hdl
unused_hdl:
// clear the exclusive monitor
clrex
bkpt #13
b hang
b unused_hdl
fiq_hdl:
// clear the exclusive monitor
clrex
bkpt #14
b hang
b fiq_hdl
......@@ -51,8 +51,6 @@ arctos_runActiveContext:
// 2) call 'hwHandleInterrupt'-function
// 3) pops the context of the new task from the new tasks stack
irq_hdl:
// clear the exclusive monitor
clrex
// lr has to be adjusted in hardware irq
sub lr, lr, #4
......@@ -96,8 +94,6 @@ irq_hdl:
// software interrupt handler
swi_hdl:
// clear the exclusive monitor
clrex
// push r0 to use the register
push {r0}
// calculate address of SWI/SVC instruction and load it into r0.
......@@ -166,8 +162,6 @@ run_cur_context:
pop {r0}
// start idle is basically the same as context_load
context_load:
// clear the exclusive monitor
clrex
// get the top of stack for the task
ldr r0, =g_cur_task_context
// move the task stack pointer into the Link Register
......
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