Commit ace420ca authored by Michael Zehrer's avatar Michael Zehrer
Browse files

changed handling of the linkerscript defined symbol '_mmu_level1_table_start_'...

changed handling of the linkerscript defined symbol '_mmu_level1_table_start_' to supress the -Warray-bounds warning
parent 80fff82d
/**
* Copyright (c) 2018, Michael Zehrer
* Copyright (c) 2018-2019, Michael Zehrer
* All rights reserved.
*
* @licence BSD
......@@ -18,6 +18,8 @@
extern "C" {
#endif
#define MMU_LEVEL1_TABLE_SIZE (4096 * 4)
typedef union {
uint32_t value;
struct {
......
/**
* Copyright (c) 2018, Michael Zehrer
* Copyright (c) 2018-2019, Michael Zehrer
* All rights reserved.
*
* @licence BSD
......@@ -17,7 +17,7 @@ extern "C" {
#endif
// defined by the linker script
extern char _mmu_level1_table_start_;
extern uint32_t _mmu_level1_table_start_[MMU_LEVEL1_TABLE_SIZE];
void _mmu_enable() {
asm volatile (
......@@ -30,9 +30,7 @@ void _mmu_enable() {
"orr r0, r0, #" STR(SCTLR_M) "\n\t"
// ... and write it back
"mcr p15, 0, r0, c1, c0, 0\n\t"
:
:
: "r0", "memory");
::: "r0", "memory");
}
void _mmu_disable() {
......@@ -43,9 +41,7 @@ void _mmu_disable() {
"bic r0, r0, #" STR(SCTLR_M) "\n\t"
// ... and write it back
"mcr p15, 0, r0, c1, c0, 0\n\t"
:
:
: "r0", "memory");
::: "r0", "memory");
}
static void createPageTableEntries(uint32_t physical_addr, uint32_t virtual_addr, uint32_t length, bool cacheable)
......@@ -61,9 +57,7 @@ static void createPageTableEntries(uint32_t physical_addr, uint32_t virtual_addr
section.bits.B = 1;
section.bits.C = 1;
}
uint32_t *level1Table = (uint32_t*)&_mmu_level1_table_start_;
// Only the top 12 bits are needed as base addresses
uint32_t virtual_base = virtual_addr >> 20;
uint32_t physical_base = physical_addr >> 20;
......@@ -72,12 +66,11 @@ static void createPageTableEntries(uint32_t physical_addr, uint32_t virtual_addr
for (; entries > 0; ++physical_base, ++virtual_base, --entries)
{
section.bits.base_address = physical_base;
level1Table[virtual_base] = section.value;
_mmu_level1_table_start_[virtual_base] = section.value;
}
// (TLBIALL) TLB Invalidate All entries (value in r0 is ignored)
asm volatile ("mcr p15, 0, r0, c8, c7, 0\n\t"
::: "memory");
asm volatile ("mcr p15, 0, r0, c8, c7, 0\n\t" ::: "memory");
}
void _mmu_init() {
......@@ -93,9 +86,7 @@ void _mmu_init() {
"mcr p15, 0, r0, c2, c0, 0\n\t"
// (TTBR1) Translation Table Base Register 1
"mcr p15, 0, r0, c2, c0, 1\n\t"
:
:
: "r0", "memory");
::: "r0", "memory");
// The complete RAM (from 0 to PERIPHERALS_BASE) could be cached
createPageTableEntries(0x00000000, 0x00000000, PERIPHERALS_BASE, true);
......
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